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 tm
TE CH
Preliminary T15M64A
SRAM
FEATURES
* High speed access time: 50/70/85/100ns * Low power supply current : - Operating : 35mA(max) - Standby : 50uA * Power supply : 5V ( 10%) * Fully static operation - No clock or refreshing required * All inputs and outputs directly LVTTL compatible * Common I/O capability * Data retention voltage : 1.5V (min) * Available packages : 28-pin DIP(600mil),SOJ, SOP, TSOP-I (8x13.4mm). * Operating temperature : 0 ~ +70 C
8K X 8 LOW POWER CMOS STATIC RAM
GENERAL DESCRIPTION
The T15M64A is a low power CMOS static RAM. organized as 8,192 x 8 bits that operates on a single 5-volt power supply. Low operating and standby current . Data retention is guaranteed at a power supply voltage as low as 1.5V. This device is packaged in a standard 28-pin DIP(600mil), SOJ, SOP, TSOP-I type.
BLOCK DIAGRAM
Vcc
VSS
A0 . . . A 12 DECODER CORE ARRAY
PART NUMBER EXAMPLES
PART NO. T15M64A-100N T15M64A-100J T15M64A-100D T15M64A-100P PACKAGE CODE
N=DIP J=SOJ D=SOP P= TSOP-I 100ns
ACCESS TIME
CS OE WE CONT ROL D AT A I/O I/O 1 . . . I/O 8
TM Technology Inc. reserves the right to change products or specifications without notice.
P. 1
Publication Date: SEP. 2002 Revision:0.A
tm
NC A 12 A7 A6 A5 A4 A3 A2 A1 A0 I/O 1 I/O 2 I/O 3 V ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14
TE CH
Preliminary T15M64A
PIN CONFIGURATION
28 27 26 25 24 V cc WE NC A8 A9 A 11 OE A 10 CS I/O 8 I/O 7 I/O 6 I/O 5 I/O 4
NC A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O 1 I/O 2 I/O 3 V ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 V cc WE NC A8 A9 A11 OE A10 CS I/O 8 I/O 7 I/O 6 I/O 5 I/O 4
D IP & SO J
23 22 21 20 19 18 17 16 15
SOP
22 21 20 19 18 17 16 15
OE A11 A9 A8 NC WE VCC NC A12 A7 A6 A5 A4 A3
1 2 3 4 5 6 7 8 9 10 11 12 13 14
TSOP-I
28 27 26 25 24 23 22 21 20 19 18 17 16 15
A10 CS I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2
PIN DESCRIPTION
SYMBOL A0 - A12 I/O1 - I/O8
CS
WE OE
Vcc Vss
DESCRIPTION Address Inputs Data Inputs/Outputs Chip Select Inputs Write Enable Output Enable Power Supply Ground
TM Technology Inc. reserves the right to change products or specifications without notice.
P. 2
Publication Date: SEP. 2002 Revision:0.A
tm
TE CH
Preliminary T15M64A
DC CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Voltage to Vss Potential Inputs to Vss Potential Power Dissipation Storage Temperature RATING -0.5 to + 7V -0.5 to Vcc +0.5 0.7 -60 to +150 UNIT V V W C
RECOMMENDED OPERATING CONDITIONS
PARAMETER Supply Voltage Input Voltage, low Input Voltage, high Ambient Temperature SYM Vcc MIN 4.5 -0.3 2.2 0 TYP 5 MAX 5.5 0.8 Vcc+0.3 +70 UNIT V V V C
VIL VIH TA
TRUTH TABLE
CS H L L L OE X H L X WE X H H L MODE Not Selected Output Disable Read Write I/O1- I/O8 High-Z High-Z Data Out Data In Power Standby Active Active Active
OPERATING CHARACTERISTICS
(Vcc = 5V / 10%, Vss = 0V, Ta = 0 ~ +70 C)
PARAMETER Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Operating Power Supply Current Standby Power Supply Current SYM. TEST CONDITIONS Vin=Vss to Vcc VI/O=Vss to Vcc , CS =VIH or
OE =
I LI I LO VOL VOH
Icc
MIN. TYP. MAX. UNIT 1 uA 2.4 1 0.4 35 30 25 20 0.3 50 uA V V mA mA mA mA mA uA
VIH or WE = VIL
I OL = + 2.1mA I OH = - 1.0mA CS =VIL , I/O=0mA
Cycle = MIN. Duty = 100% -50 -70 -85 -100
I SB I SB1
CS=VIH , Cycle=min, Duty=100%
CS Vcc -0.2V
TM Technology Inc. reserves the right to change products or specifications without notice.
P. 3
Publication Date: SEP. 2002 Revision:0.A
tm
TE CH
Preliminary T15M64A
CAPACITANCE
(Vcc = 5V / 10%, Ta = 25C, f = 1 MHz)
PARAMETER Input Capacitance Input/ Output Capacitance SYMBOL CONDITION VIN = 0V VOUT = 0V MAX. 6 8 UNIT pF pF
C IN C I/O
Note: These parameters are sampled but not 100% tested.
AC TEST CONDITIONS
PARAMETER Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Output Load 0V to 3V 3 ns 1.5V See Fig. 1,2 CONDITIONS
AC TEST LOADS AND WAVEFORM
5V OUTPUT
R1 - 1928 ohm
5V OUTPUT
R1- 1928 ohm
30pF Including Jig and Scope
R2 1020 ohm
5pF Including Jig and Scope
R2 1020 ohm
(For TCLZ, TOLZ, TCHZ, TOHZ, TW H Z , TOW )
Fig 1
Fig 2
TM Technology Inc. reserves the right to change products or specifications without notice.
P. 4
Publication Date: SEP. 2002 Revision:0.A
tm
TE CH
Preliminary T15M64A
AC CHARACTERISTICS
(Vcc = 5V / 10%, Vss = 0V, Ta =0 ~ +70 C)
(1) READ CYCLE
PARAMETER Read Cycle Time Address Access Time Chip Select Access Time Output Enable to Output Valid Chip Selection to Output in Low Z Output Enable to Output in Low Z Output Disable to Output in High Z Output Hold from Address Change SYM.
-50ns
MIN MAX
-70ns
MIN. MAX.
-85ns
-100ns
UNIT
MIN. MAX. MIN. MAX.
tRC tAA tACS tAOE tCLZ* tOLZ* tOHZ* tOH
50 7 5 10
50 50 25 20 20 -
70 10 5 10
70 70 35 25 25 -
85 10 5 10
85 85 40 30 30 -
100 10 5 10
100 100 50 30 30 -
ns ns ns ns ns ns ns ns ns
Chip Deselection to Output in High Z tCHZ*
* These parameters is measured with 5pF test load.
(2)WRITE CYCLE
PARAMETER Write Cycle Time Chip Selection to End of Write Address Valid to End of Write Address Setup Time Write Pulse Width Write Recovery Time Data Valid to End of Write Data Hold from End of Write Write to Output in High Z Output Active from End of Write SYM.
-50ns
MIN
-70ns
-85ns
-100ns
UNIT ns ns ns ns ns ns ns ns ns ns
MAX MIN. MAX. MIN. MAX. MIN. MAX.
tWC tCW tAW tAS tWP tWR tDW tDH tWHZ* tOW
50 40 40 0 30 0 25 0 5
20 -
70 60 60 0 50 0 30 0 5
25 -
85 70 70 0 60 0 35 0 5
30 -
100 80 80 0 70 0 40 0 5
30 -
* These parameters is measured with 30pF test load.
TM Technology Inc. reserves the right to change products or specifications without notice.
P. 5
Publication Date: SEP. 2002 Revision:0.A
tm
TE CH
Preliminary T15M64A
Symbol VDR IDR Test Condition CS Vcc -0.2V
Vcc =5.0, CS Vcc -0.2V
DATA RETENTION CHARACTERISTICS
Item Vcc for data retention Data retention current Recovery time Min 1.5 0 5 Typ max 50 unit V uA ms
Data retention set-up time tCDR
tR
See data retention waveform
DATA RETENTION WAVE FORM
Data Retention M ode
V CC
V cc_typ
t
V D R > 1.5V
Vcc_TYP t
CD R
R
CS
CS >VCC-0.2V
V IH V IH
TM Technology Inc. reserves the right to change products or specifications without notice.
P. 6
Publication Date: SEP. 2002 Revision:0.A
tm
(Address
TE CH
Preliminary T15M64A
TIMING WAVEFORMS READ CYCLE 1
Controlled)
tR C
A d d re s s
tA A tO H tO H
DOUT
READ CYCLE 2
(Chip Select
CS
tA C S tC L Z tC H Z
Controlled)
DOUT
READ CYCLE 3
(Output Enable Controlled)
tR C
A d d re s s
tA A
OE
tA O E tO L Z tO H
CS
tA C S tC L Z tO H Z tC H Z
DOUT
DON' T CARE UNDEF INED
TM Technology Inc. reserves the right to change products or specifications without notice.
P. 7
Publication Date: SEP. 2002 Revision:0.A
tm
Ad d r es s
TE CH
( OE CLOCK)
tW C
Preliminary T15M64A
WRITE CYCLE 1
t
WR
OE
tC W
CS
t t AW WP
WE
t AS (1,4)
tO H Z
DOUT
t DW t DH
DIN
WRITE CYCLE 2
( OE = V
IL
Fixed)
tW C
A d d re s s
tC W tW R
CS
tA W tW P
WE
tA S tW H Z (1 ,4 ) tO W
tO H
(2 )
(3 )
DOUT
tD W tD H
D IN
DON'T CARE UNDEF INED
TM Technology Inc. reserves the right P. 8 to change products or specifications without notice.
Publication Date: SEP. 2002 Revision:0.A
tm
TE CH
Preliminary T15M64A
Notes: 1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied. 2. The data output from D OUT are the same as the data written to D IN during the write cycle. 3. D OUT provides the read data for the next address. 4. Transition is measured 500 mV from steady state with C L = 5pF. guaranteed but not 100% tested. This parameter is
5. If OE is low during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is high during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
TM Technology Inc. reserves the right P. 9 to change products or specifications without notice.
Publication Date: SEP. 2002 Revision:0.A
tm
TE CH
Preliminary T15M64A
PACKAGE DIMENSIONS 28-LEAD DIP SRAM (600 mil)
A
A1
D
B2 B B3 B1 C2 C1 C D1
Symbol A A1 B B1 B2 B3 C C1 C2 D D1
Dimension in inches min. typ. max 1.440 0.546 0.100 0.140 0.015 0.016 0.600 0.630 1.450 0.550 0.210 0.150 0.100 0.018 0.060 0.612 0.650 1.460 0.554 0.160 0.020 0.624 0.670
Dimension in mm min. typ. max. 36.58 13.87 2.54 3.56 0.38 0.41 15.24 16.0 36.83 13.97 5.33 3.81 2.54 0.46 1.52 15.54 16.51 37.08 14.07 4.06 0.51 15.85 17.0
Publication Date: SEP. 2002 Revision:0.A
TM Technology Inc. reserves the right P. 10 to change products or specifications without notice.
tm
TE CH
Preliminary T15M64A
PACKAGE DIMENSIONS 28-LEAD SOJ SRAM (300 mil)
SYMBOL A B C D E F G H I J K L M N O P Q y
DIMENSIONS IN INCHES 0.7100.002 0.3000.005 0.0600.002 0.0500.001 0.0630.001 0.0150.002 0.0300.002 0.0500.002 0.0180.002 0.0280.002 0.3370.002 0.0100.001 0.0260.002 0.2680.003 0.3000.002 0.0530.001 0.1400.004 0.004(MAX)
DIMENSIONS IN MM 18.030.05 7.620.13 1.520.05 1.270.03 1.630.03 0.380.05 0.760.05 1.270.05 0.460.05 0.710.05 8.560.05 0.250.03 0.660.05 6.810.08 7.620.05 1.350.03 3.560.10 0.10(MAX)
TM Technology Inc. reserves the right P. 11 to change products or specifications without notice.
Publication Date: SEP. 2002 Revision:0.A
tm
TE CH
Preliminary T15M64A
PACKAGE DIMENSIONS 28-LEAD SOP
e1 28 15
E HE
Detail F 1 D A2 S y Seating Plane e A1 See Detail F A LE b 14 L e1 C
Symbol A A1 A2 b C D E e HE L LE S y
Dimension in inches Dimension in mm min. typ. max min. typ. max. 0.112 2.845 0.004 0.102 0.093 0.098 0.103 2.362 2.489 2.616 0.014 0.016 0.020 0.335 0.406 0.508 0.008 0.010 0.014 0.203 0.254 0.356 0.713 0.733 18.110 18.618 0.326 0.331 0.336 8.280 8.407 8.534 0.044 0.050 0.056 1.118 1.270 1.422 0.453 0.465 0.477 11.506 11.811 12.116 0.028 0.036 0.044 0.711 0.914 1.117 0.059 0.067 0.075 1.499 1.702 1.905 39 1.0 0.004 0.102 0 10 0 10
Notes : 1. Dimensions D max. & S include mold flash or tie bar burrs. 2. Dimension b does not include dambar protrusion / intrusion. 3. Dimensions D & E include mold mismatch and determined at the mold parting line. 4. controlling dimension : inches 5. general appearance spec should be based on final visual inspection spec.
TM Technology Inc. reserves the right P. 12 to change products or specifications without notice.
Publication Date: SEP. 2002 Revision:0.A
tm
1
TE CH
Preliminary T15M64A
PACKAGE DIMENSIONS 28-LEAD TSOP-I (8X13.4mm)
D C 28 b E e 14 15 A2 "A" A A1 Seating plane y
Db Gauge plane Seating plane L
0.010
Detail "A"
L1
SYMBOL A A1 A2 b c Db E e D L L1 y
DIMENSIONS IN INCHES 0.047(max.) 0.0040.002 0.0390.002 0.008(typ.) 0.006(typ.) 0.4650.004 0.3150.004 0.022(typ.) 0.5280.008 0.0200.004 0.03150.004 0.004(max.) 0~5
DIMENSIONS IN MM 1.20(max.) 0.100.05 1.000.05 0.20(typ.) 0.15(typ.) 11.800.10 8.000.10 0.55(typ.) 13.400.20 0.500.10 0.800.10 0.10(max.) 0~5
TM Technology Inc. reserves the right P. 13 to change products or specifications without notice.
Publication Date: SEP. 2002 Revision:0.A


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